The industry-reference IP Core provider of Turbocodes and LDPC solutions
TurboConcept logo
  • Home
  • Products
  • Services
  • About us
  • Contact

  • Latest news

    High throughput / Low latency Viterbi decoder for LTE, WiFI and WCDMA
    June 19th, 2017

    New Flexible LDPC encoder/decoder Cores
    June 19th, 2017

    LTE Cat-0 turbo decoder now available
    May 17th, 2016

    2.5 Gbit/s DVB-S2X FEC encoder now available
    February 2nd, 2016


    View more...

    Contact us
    for more information info@turboconcept.com

    Tel: +33 2 98 05 63 80

    Products > Broadband wireless > tc1750

    4G multi-mode encoder

    Product code: TC1750

    TC1750 is a high throughput turbo/convolutional code encoder covering LTE, HSPA+, WiMAX 16e/m. It performs either convolutional turbo code (CTC) encoding or convolutional code (CC) encoding and rate matching for these three PHY layer specifications.

    The rate matching is flexible and can easily be used to execute HARQ mechanism. Thanks to its high throughput architeture TC1750 is able to reach multi-Gbits/s throughput ranges with a single core instance:

    • up to 4 Gbits/s payload rate in LTE mode (with 500 MHz clock)
    • up to 1 Gbits/s payload rate in HSPA mode (with 500 MHz clock)
    TC1750 can be used for both uplink and downlink. It can be implemented in Base Stations (from femtocells to large stations) or in the terminal SoC. ASIC and FPGA versions are available.

    Functional coverage:

    The core is not a simple turbo encoder accelerator, but offers the support of rate matching functions (see below) that off-loads the DSP from this tasks without requiring an additional hardware module.

    • 3GPP LTE mode
      • CRC encoding
      • CTC block sizes range: 40 to 6144 bits
      • CC block sizes: 8 to 1024 bits
      • rate matching: bit collection, sub-block interleaving, bit selection
    • 3GPP-HSPA+ mode
      • CTC block sizes range: 40 to 5114 bits
      • CC block sizes range: 8 to 504 bits
      • rate-matching: bit separation, puncturing / repetition, bit collection
    • IEEE802.16d/e/m WiMAX mode
      • CRC encoding
      • CTC block sizes: 48 to 4800 bits
      • CC block sizes: 48 to 288 bits
      • rate matching: sub-block interleaving, bit grouping, bit selection

    Features:

    • Block-by-block change of physical layer mode (LTE/HSPA+/WiMAX), block length, rate matching parameters
    • Latency reduction by bank swapping
    • No external memory required
    • High throughput architecture
    • Silicon proven
    • ASIC Core: Verilog or VHDL RTL source code
    • FPGA Core available on all popular Altera, Lattice and Xilinx devices

    Related Cores: