The industry-reference IP Core provider of LDPC, Polar and Turbo solutions
TurboConcept logo
  • Home
  • Products
  • Services
  • About us
  • Contact

  • Latest news

    TurboConcept and Lomicro Information Technology today celebrate two years of successful collaboration
    April 3rd, 2023

    New IP Core available : LTE/NR small block lengths decoder
    March 30th, 2023

    TurboConcepts successfully completes research project FlexDEC-5G for designing FEC decoders for 5G
    October 2nd, 2020

    Improved 5G LDPC and Polar solutions are available from TurboConcept for FPGA and ASIC implementation.
    January 27th, 2020


    View more...

    Contact us
    for more information info@turboconcept.com

    Products > Broadband wireless > tc7100

    3GPP WCDMA turbo decoder

    Product code: TC7100

    TC7100 is a convolutional turbo code (CTC) decoder supporting 3GPP specifications. The Core is self-contained and does not require external memory banks. The decoded throughput is typically 40 Mbits/s. The Core is available for FPGA or ASIC implementation, and is silicon-proven.

    Functional coverage:

    Compliant with 3GPP WCDMA specifications (26.212 and 26.222):

    • 8-states binary turbo code with tails bits for trellis termination
    • block size: from 40 to 5114 bits with bit granularity
    • code rate 1/3

    Features

    • Flexible pipe-line architecure for efficient architecture for both FPGA and ASIC
    • Very high clock frequency profile for FPGA
    • Near floating point error correction performance
    • Selection between Max-Log-MAP and Log-MAP algoritms
    • Efficient iteration stopping feature for reducing average number of iterations
    • On-the-fly change of block length and number of iterations
    • Single FPGA Core (no external memory required), available on all popular Xilinx, Altera and Lattice devices
    • ASIC Core: Verilog or VHDL RTL Core delivery
    • Silicon-proven

    Related Cores:

    • HSPA encoder Core covering CTC encoding + rate-matching (TC7100enc)