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    About us > News > 2020

    2020

    Improved LDPC and Polar solutions are available from TurboConcept for FPGA and ASIC implementation.

    Our wireless products have been further optimized in the frame of the FLEXDEC-5G project partially funded by the European Union through FEDER

    2018

    5G LDPC and Polar solutions are available from TurboConcept for FPGA and ASIC implementation.

    Our products have been extensively tested and validated with several early adopters during H1/2018 and have reached production-level maturity. We propose a comprehensive set of hardware accelerators for LDPC and Polar encoding/decoding. Our products are scalable in throughput and functional coverage, and offer a full set of ancillary features to meet the most demanding SoC requirements.

    2017

    5G implementations for LDPC and Polar encoder/decoder Cores are being ready as the 3GPP specification finalizes. Our Cores cover FEC, Rate matching, HARQ combining and CRC check. Please contact us to receive more information.

    A new Viterbi decoder Core covering LTE and WiFi (and optionally WCDMA) (TC1720) is available from TurboConcept. The Core offers a comprehensive functional coverage including rate matching, Viterbi decoding and CRC check for both WiFi and LTE phy layers. The Core implements a new architecture allowing to reach very efficient throughput and latency levels with a small silicon area. The Core is silicon proven.

    Addressing early 5G applications, a flexible LDPC encoder / decoder Core covering a very large range of quasi-cyclic LDPC codes (TC5100) is now available. The Core covers essentially all possible Quasi-Cyclic LDPC codes, with expansion factors ranging from 2 to 1024 and arbitrary base graph. The Core integrates ancillary functions : a flexible rate matching scheme, HARQ combining, soft-output and channel quality estimation.

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