DVB-RCS turbo decoder Product code: TC1000

TC1000 implements the turbo code specified by DVB-RCS for Interactive 2-way satellite systems. This turbo code offers a very high flexibility in terms of block size and code rate combinations, enabling efficient multi-user systems and low latencies. TurboConcept's TC1000 encoder/decoder Cores gives optimal throughput versus FPGA resource usage trade-offs. The typical DVB-RCS usage is in the hub (base-station), where a single high-throughput decoder Core can be shared by many users and frequency bands. Implemented in low-cost FPGA devices or in an ASIC, the Core is also an efficient solution at terminal side. TC1000 is the industry reference and equips today most of the RCS or RCS-like systems.

FEC technology:

• Two dimensional Parallel concatenation of Convolutional Codes, 8 states
• Duo-binary (trellis constructed with a pair of input bits at each encoding cycle)
• Flexible block size (16 to 216 payload bytes, can be extended to higher or custom sizes)
• Flexibility in coding rate (1/3, 2/5, 1/2, 2/3, 3/4, 4/5, 6/7)
• Good BER performance for short to medium block size

Features:

• Full DVB-RCS coverage
• Custom block size / code rates available
• Three throughput levels available ("2X","4X" or "8X"), 40 to 120 Mbps at 5 iterations
• Advanced architecture - low complexity
• Selectable quantization width - 3 to 8 bits
• Single FPGA Core, available on all popular Xilinx and Altera devices
• On-the-fly (Block-by-block) change of code rate, block size, number of iterations
• Latency reduction by bank-swapping (2 input buffers)
• In-operation BER monitoring
• Micro-controller interface

Related Cores:

• DVB-RCS turbo encoder (TC1000enc)
• DVB-RCS2 turbo decoder (TC1620)