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    Products > Broadband wireless > tc7100

    3GPP WCDMA turbo decoder

    Product code: TC7100

    TC7100 is a convolutional turbo code (CTC) decoder supporting 3GPP specifications. The Core is self-contained and does not require external memory banks. The decoded throughput is typically 40 Mbits/s. The Core is available for FPGA or ASIC implementation, and is silicon-proven.

    Functional coverage:

    Compliant with 3GPP WCDMA specifications (26.212 and 26.222):

    • 8-states binary turbo code with tails bits for trellis termination
    • block size: from 40 to 5114 bits with bit granularity
    • code rate 1/3


    • Flexible pipe-line architecure for efficient architecture for both FPGA and ASIC
    • Very high clock frequency profile for FPGA
    • Near floating point error correction performance
    • Selection between Max-Log-MAP and Log-MAP algoritms
    • Efficient iteration stopping feature for reducing average number of iterations
    • On-the-fly change of block length and number of iterations
    • Single FPGA Core (no external memory required), available on all popular Xilinx, Altera and Lattice devices
    • ASIC Core: Verilog or VHDL RTL Core delivery
    • Silicon-proven

    Related Cores:

    • HSPA encoder Core covering CTC encoding + rate-matching (TC7100enc)