Products > Domestic & PLC networks > tc1400

TC1400 is a turbo decoder supporting the three following specifications Homeplug AV 1.0, Homeplug AV 2.0 and IEEE1901.

The core is available with two levels of throughputs:

• high throughput profile: up to 1 Gbits/s on high end process nodes
• low throughput profile: 200 Mbits/s @ 8 iteration on high end process nodes

Thanks to its flexible pipe-line architecture, TC1400 can be implemented efficiently on both ASIC and FPGA.

Functional coverage:

The following functions are supported:

• channel de-interleaving
• depuncturing for code rates 1/2, 16/21 and 16/18
• turbo decoding for payload block sizes 16, 32, 136 and 520 bytes

Features:

• Flexible pipe-line architecture for best efficiency on ASIC and FPGA targets
• Efficient early stopping capability for reducing average number of iterations (reduced power consumption, higher average throughput)
• Block-by-block change block length, and number of iterations
• Latency reduction by bank swapping
• No external memory required
• Channel BER estimator
• Selectable quantization level - prior synthesis (4 to 8 bits LLR quantization)
• Low power architecture
• Silicon proven
• ASIC Core: Verilog or VHDL RTL source code
• FPGA Core available on all popular Altera, Lattice and Xilinx devices

Related Cores:

• Homeplug AV CTC encoder (TC1400enc)