The industry-reference IP Core provider of LDPC, Polar and Turbo solutions
TurboConcept logo
  • Home
  • Products
  • Services
  • About us
  • Contact

  • Latest news

    TurboConcept and Lomicro Information Technology today celebrate two years of successful collaboration
    April 3rd, 2023

    New IP Core available : LTE/NR small block lengths decoder
    March 30th, 2023

    TurboConcepts successfully completes research project FlexDEC-5G for designing FEC decoders for 5G
    October 2nd, 2020

    Improved 5G LDPC and Polar solutions are available from TurboConcept for FPGA and ASIC implementation.
    January 27th, 2020

    View more...

    Contact us
    for more information

    Products > Broadband wireless > tc5200

    5G LDPC encoder/decoder

    Product code: TC5200

    TC5200 is an efficient LDPC encoder/decoder Core solution fully compliant with 3GPP NR (5G) specifications. The Core is fully validated and has been selected by several early adopters for their 5G SoC.


    • 3GPP NR (5G) base station
    • 3GPP NR (5G) terminal
    • WiFi compliant

    Functional specifications (encoder):

    • CRC encoding
    • Filler bits insertion/removal
    • LDPC encoding (basegraph1 and 2, all Z-values)
    • Rate matching (incl. repetition)
    • Bit-level interleaver
    • Support of WiFi (optional)
    • Transport Block level processing (optional)

    Functional specifications (decoder):

    • Bit-level de-interleaver
    • HARQ combining
    • Inverse Rate matching (incl. repetition)
    • Filler bits insertion/removal
    • LDPC decoding (basegraph1 and 2, all Z-values)
    • CRC decoding
    • Soft-output interface (optional)
    • Support of WiFi (optional)
    • Reencoded output stream (optional)
    • Transport Block level processing (optional)

    Core features:

    • Fully validated Cores (comprehensive factory tests, independant verifications)
    • Advanced HARQ combining / stream compression
    • Versatile Decoding algorithm profiles
    • Scalable throughput design
    • Very high clock frequency achieved on ASIC process
    • Multi-Gigabit range throughput
    • Scalable design (three throughput profiles)
    • AXI4-stream interfaces
    • Frame-by-frame on-the-fly configuration
    • Comprehensive monitoring information (syndrome check, SNR indicator,...)
    • Efficient iteration-stopping feature

    Related Cores: